• Shorten Time to Gain Confidence in the Test System Setup
• Front-panel LEDs provide Status Information such as Link Speed, Symbol Lock, and Link Activity
• Auto-configure sets up the Logic Protocol Analyzer System to be Ready for Data Acquisition Quickly
• FastSYNC Tracks the Link as it Transitions In and Out of ASPM Power States such as L0s, Regardless of Electrical Idle Duration
• Real-time Statistics Help Observe Link Health and Behavior over Time
• Powerful Trigger-state Machine Spans All Layers of the Protocol
• 8 States, 8 Packet Recognizers
• 4 Symbol Sequence Recognizers, 4 Counter/Timers, 4 Event Flags
• 4 Symbol Sequence Recognizers
• Conditional Storage
• Industry's Deepest 8 GB Memory/Module (16 GB memory, x16 link width) Increases the Chances of Capturing an Error and the Fault that Caused the Error
• HW Accelerated Search and Data Displays provide Immediate Visibility of Data Regardless of Record Length
• Information Density for Rapid Data Analysis
• The Transaction Window provides Visibility into Protocol Behavior at the Packet and Transaction Level interspersed with Physical Layer Activity
• The Summary Profile Window Helps Ascertain the Health of the System and Identify Patterns of Interest such as Errors, TLPs, DLLPs, Ordered Sets, etc.
• Multibus Visibility for System-level Debug
• Analyze Complete System Interactions with Time-correlated, Multibus Analysis on a Single Display in a Single Mainframe. For example, Tracing Memory Access from PCI Express to DDR Memory
• Cross Triggering and a Common Global Time Stamp enables Accurate and Efficient Debugging by Showing Exactly What Was Happening on One Bus Relative to Another at Any Given Instant in Time

Applications

• PCI Express Debug from Protocol Layer to Physical Layer
• Silicon Validation
• Computer System Validation
• Embedded System Debug and Validation
• Processor/Bus Debug and Verification
• Embedded Software Integration, Debug, and Verification

Tektronix PCI Express Logic Protocol Analyzer: A Complete Solution for Physical through Protocol Layer Debug.
The TLA7SA00 Series Logic Protocol Analyzer modules for the TLA7000 Series deliver the speed you need to capture the source of those elusive problems, plus the visibility you want with large displays and fast system data throughput, while protecting your investment with compatibility with all other TLA modules for cross bus-timing correlation.

Features & Benefits

• PCI Express Gen1 through Gen3 including Gen3 Protocol to Physical Layer Analysis for Link Widths from x1 through x16 with up to 8.0 GT/s Acquisition Rates
• Comprehensive PCI Express Probing Solutions, including Midbus, Slot Interposer, and Solder-down Probes
• Nonintrusive Probing that Utilizes OpenEYE Technology incorporating Automatic Tuning Equalization Circuitry to allow Probing Anywhere on the Channel and Ensure Accurate Data Capture in PCI Express Systems with Channel Lengths up to 24 in. and 2 Connectors
• ScopePHY provides the ability to Quickly Connect Any of the PCI Express Midbus, Slot Interposer, or Solder-down Probes to a High-performance Oscilloscope providing a More Detailed Analog View of the PHY Layer

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