SATA Protocol Test System

Serial ATA Test and Verification: Teledyne LeCroy’s protocol analysis tools are designed from the ground up to address these unique characteristics of Serial ATA. Teledyne LeCroy’s analysis and design suites are developed specifically for use with the SAS and SATA protocols, and provide extensive protocol decoding, expert error analysis, and complete user support when decoding and viewing the recorded traffic. This extensive protocol support, combined with the different traffic views, advanced triggering, data filtering, traffic generation, and error injection capability, allows engineers to rapidly become familiar with SATA-specific issues, and quickly understand new issues the first time they encounter them.

Teledyne LeCroy provides everything needed for Serial ATA analysis including real-time hardware triggering and filtering on the critical components of Serial ATA traffic. Teledyne LeCroy’s Expert Analysis software simplifies the overall debug process by using collapsible, color-coded packets to represent commands, FISs and primitives. This provides point-and-click “drill down” to lower level details along with the ease of use and understanding that Teledyne LeCroy is well known for.

Learn more about SATA (Serial ATA)Technology

SATA (Serial ATA) Overview

The storage industry is in the midst of a large-scale transition from parallel ATA, the dominant desktop storage interface, to Serial ATA. This migration reflects a broader transition across the industry to Serial technologies for computer-based communications. Driven primarily by lower voltages and costs required in future chipsets, Serial ATA is poised for industry-wide adoption. The specification thoughtfully preserves software compatibility with the Parallel ATA command set. What’s more, it offers smaller, thinner, lower cost cables that also offer compatibility at the physical layer with the emerging Serial Attached SCSI (SAS) standard.

Features

Performance

Lower Voltage

Pin Count

Improved Cabling

Software Compatible

SAS Compatibility

SATA DevSleep™

Architecture

Serial ATA is a full duplex protocol. There is a continuous flow of signals from each device moving down the bus. The device and host are transmitting (TX) and receiving (RX) at the same time.

Bidirectional traffic pattern eliminates the need for bus negotiation overhead

Data characters vs Primitives – Primitives are the simplest elements within the Serial ATA protocol. Primitives are 32-bit DWORDs used to initiate control of the serial line functions (X_RDY, CONT, etc…). In addition to these “handshaking” and flow control signals, Primitives are also used to delimit or “frame” user data.

Frame Information Structure (FIS) – A frame is an indivisible unit of information exchanged between a host and device. A frame consists of a SOF primitive, a Frame Information Structure (FIS), a CRC calculated over the contents of the FIS, and an EOF primitive. A FIS is the user payload of a frame; a frame is a group of Dwords that convey information between host and device as described previously.

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